library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity muxbus is
	port (
		sel  : in std_logic_vector(1 downto 0);
		A: in std_logic_vector(47 downto 0);
		B: in std_logic_vector(47 downto 0);
		C: in std_logic_vector(47 downto 0);
		D: in std_logic_vector(47 downto 0);
		rd0: in std_logic;
		rd1: in std_logic;
		rd2: in std_logic;
		rd3: in std_logic;
		clock: in std_logic;
		result : out std_logic_vector(47 downto 0));
end muxbus;

architecture RTL of muxbus is
signal s: std_logic_vector(47 downto 0);
signal rd : std_logic;
begin
	process(clock)
	begin
		if (clock'event and clock = '1') then
		rd <= rd0 or rd1 or rd2 or rd3; 
		if (rd = '0') then 
			s <= (others=>'0');
		else if (sel="00") then
				s <= A;
			elsif (sel="01") then
				s <= B; 
			elsif (sel="10") then 
				s <= C;
			elsif (sel="11") then
				s <= D;
			end if;
		end if;
		result <= s;
 		end if;
	end process;
end RTL;